Embodiments of the present invention generally relate to a device and method for controlling self-refresh, and more particularly to a technology for reducing a current when a semiconductor device is in a self-refresh operation.
Generally, in a memory unit of a dynamic random access memory (DRAM), a plurality of unit cells each of which contains one transistor and one capacitor, is configured in the form of a matrix in a manner where the unit cells are arranged in a plurality of rows and columns. Addresses designate such rows and columns, and commands for performing the read/write operation in each cell unit are provided to such addresses.
A DRAM cell stores charge-type data in a cell, but due to material limitations of silicon requisite for cell fabrication, the data needs to be periodically recharged to prevent data loss.
Data stored in a DRAM cell is recharged by eliminating leakage current, sensing and amplifying the data of the cell, and rewriting the sensed and amplified data back into the cell. This recharge operation is referred to as a refresh operation.
Effectively, the refresh operation reads data from the DRAM cell, amplifies the read data, and re-stores the amplified data. The refresh operation is performed by a bit line sense amplifier (sense-amp) located close to a memory cell array.
The refresh operation begins when a refresh command is received, after which one of a plurality of rows contained in a unit cell array is selected on the basis of a row address activated by the refresh command.
As a corresponding word line of the selected row is charged with a constant potential, all cells connected to the selected row are activated, and data is transmitted to a bit line through an activated cell. Data is amplified due to the operation of the bit line sense-amplifier, and is subsequently stored in the selected cell.
The most representative refresh methods for synchronous DRAMs are classified into an auto-refresh method and a self-refresh method. In an auto-refresh method, an auto-refresh operation is performed through an external terminal of a synchronous DRAM chip at a predetermined time.
However, in a self-refresh method, when a command is provided, a subsequent refresh operation is automatically carried out in response to an indication message from a timer embedded in a chip.
A method for entering the self-refresh mode in the synchronous DRAM is synchronized with a clock signal. That is, an entry mode is determined by external signals such as a RAS bar signal (RAS#), a CAS bar signal (CAS#), a column selection signal (CS#), a clock enable signal (CKE), etc. at a positive edge of the clock signal.
However, there is a need for a condition capable of terminating a self-refresh operation either after the refresh operation is executed on the basis of a constant internal period during the self-refresh operation, or at any time during the refresh operation. That is, during the self-refresh operation, internal operations of the chip are asynchronously operated and are not affected by external clocks.
Particularly, the self-refresh termination operation is achieved by deactivation of a pin of a clock enable signal (CKE). Therefore, the self-refresh termination operation is asynchronously achieved.
A method for terminating the self-refresh operation is also achieved by reactivation of a clock enable signal. That is, as the clock enable signal is activated, the external clock signal is re-applied to the chip, and the chip operation is re-affected by the external clock signal. After completion of the self-refresh operation, a predetermined delay time elapses, and subsequently another operation starts.
The operation intervals of the self-refresh mode can be classified into a first operation interval, a second operation interval, and a third operation interval. According to the first operation interval, the synchronous DRAM is synchronized with the clock signal to enter the self-refresh mode. According to the second operation interval, the internal refresh operation of the synchronous DRAM is asynchronously performed. According to the third operation interval, the synchronous DRAM is asynchronously terminated.
Since how long a mobile product can function with an embedded battery is an important factor in the product, it is very important for a mobile DRAM mounted to such products to reduce a self-refresh current generated in a DRAM standby state.